Delay Optimisation in High - Performance Carry - Select Adders
نویسنده
چکیده
This paper analyses techniques to measure the delay of 64 bit and 128-bit carry select adders .This is used for high-performance and low-power applications. It is introduced to work at a lower time delay than that required by a Ripple Carry Adder. This paper uses a very simple and efficient gate-level modification technique to significantly reduce the delay of the CSA. The proposed design has reduced delay and is compared with the 64 bit CSA. Xilinx ISE is used for simulation and synthesis.
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